Analogue to digital converter

ABSTRACT

In an analogue to digital converter the unknown voltage is applied continuously to an integrating circuit during each conversion period. An opposing reference voltage is switched on and off to cause the amplifier output to ramp up and down between two detection levels. One or both of these levels varies as a periodic function of time, e.g. a sawtooth waveform. Clock pulses are counted when the slope of the output ramp is of one sign only and it is shown that the ratio of the unknown voltage to the reference voltage is simply related to the number of clock pulses actually counted when the slope is of said one sign and the total number of clock pulses occurring during the conversion period.

.Iadd.This application is a continuation of application Ser. No.769,588, filed on Oct. 22, 1968, and now abandoned. .Iaddend.

The invention relates to an analogue to digital converter (ADC) andconcerns a converter which converts an analogue quantity to acorresponding digital count, by counting clock pulses during aparticular time interval. A use of such converters is as voltmeters.

One well known ADC is the dual ramp type in which the unknown voltage isapplied to an integrating amplifier for a fixed period of time definedby a number of clock pulses. The unknown voltage is then removed and areference current is fed into the amplifier to restore the output todatum. The number of clock pulses counted while the reference currentflows is proportional to the unknown voltage. It will be apparent thatthe total time for a measurement depends upon the magnitude of theunknown voltage. This means that measurements taken cyclically musteither be taken at a variable rate, which is frequently undesirableowing to the need to synchronise the operation of the ADC with otherequipment, or at a relatively slow fixed rate determined by the cycletime required for measuring a full scale input. There will then normallybe wasted waiting time in each cycle and in any case the dual ramp ADCrequires the unknown voltage to be applied for the first part only ofeach cycle. It is frequently desirable to be able to accept the unknownvoltage continuously in order for example to overcome transientfluctuations caused by the switching operation. In practice this mayobviate the need for a buffer amplifier.

In the specification of U.S. Pat. No. 3,267,458 there is described anADC which will accept the unknown voltage continuously. To this end,whenever the output of the integrating amplifier exceeds a giventhreshold level a standard increment of charge is fed into the amplifierin opposition to the current flowing in response to the unknown voltage.The number of such increments counted in a given interval isproportional to the unknown voltage. This ADC is however subject to thedisadvantage that a large number of current pulses may have to beswitched into the amplifier and counted in some instances. Thecumulative switching errors are sometimes substantial and limit theaccuracy and resolution of the ADC.

There is also described an ADC in the specification of copending U.S.application Ser. No. 481,853 filed Aug. 23, 1965, now U.S. Pat. No.3,458,809, issued July 29, 1969, which will operate cyclically andaccept a continuous input. The increments of charge are fed in at astandard rate during part only of each cycle, the two parts of the cyclebeing demarcated by the time at which the amplifier output attains afixed trigger level. After some such cycles the system stabilizes andthe mark to mark-plus-space ratio of each cycle represents the magnitudeof the unknown voltage. The ADC illustrated and described in the lastsaid specification is sometimes also subject to the disadvantage ofswitching large numbers of increments of charge.

In contrast with such prior art the present invention opens up thepossibility of an entirely new mode of operation which permits a singlemeasurement to be made in one cycle of predetermined duration and yetonly requires a relatively small number of switching operations percycle.

According to the present invention there is provided an analogue todigital converter comprising an integrating means arranged to integratefirst and second opposing electrical signals, of which one is derivedfrom an unknown signal and the other is a reference signal. A bistabledevice controls the second signal which is integrated by the integratingmeans in one state only of the bistable device, while the first signalis integrated continuously, at least during the course of a measurementcycle. Level detection means are responsive to and arranged to detecttwo distinct levels of the output signal of the integrating means and socontrol the bistable device that, when the output signal reaches onelevel the bistable device is switched to its one state, whereupon theoutput signal returns towards the other detection level and when itreaches the other detection level the bistable device is switched to itsother state and the output signal returns towards the said one level.The converter further comprises means for applying a variable waveformsignal to the level detection means to cause at least one of the levelsdetected thereby to vary, and means for counting clock pulses while thebistable device is in one only of its two states. The means for applyinga variable waveform signal may be merely a switch to cause the levelsdetected by the level detector to switch from one discrete level toanother, or it may be a more complex circuit for causing the level tovary in some predetermined manner with time.

Assuming that a continuous measurement is required the signal derivedfrom the unknown signal will be the first, continuously integratedsignal and the reference signal will be switched by the bistable,(although the converse situation is theoretically usable).

Preferably one of the detection levels or both such levels vary in acontinuous, rather than a stepwise, manner. This gives rise to twodistinct modes of operation, determined by whether the two levelsconverge or diverge. In the divergent mode it is desirable that the, oreach, detection level varies periodically. Otherwise the stabilizationover several cycles may not take place. In the convergent mode cyclicoperation is not essential, but is usually desirable. In either mode itwill normally be necessary to have the two levels converge to or divergefrom a condition of equality and in ordinary applications both levelswill be linear functions of time (which includes the case where onelevel is constant).

It can always be arranged that there is a free portion at the beginningof a cycle before the counter is called upon to start counting clockpulses and this free portion can be used to display or read out thecount attained during the preceding cycle. The cycles can thus followeach other immediately with completely continuous monitoring of anunknown voltage.

These various features and advantages will be better understood from thefollowing more detailed description, given by way of example, withreference to the accompanying drawings, in which:

FIG. 1 is a block diagram of one embodiment of the invention,

FIG. 2 shows voltage waveforms illustrating operation in the convergentmode,

FIG. 3 shows voltage waveforms illustrating operation in the convergentmode with both detection levels varying, and

FIG. 4 shows voltage waveforms illustrating operation in the divergentmode.

In FIG. 1 the unknown voltage V_(U) applied to a terminal 10 feedscurrent continuously through a resistor R₁ into an integratingoperational amplifier 11 having a feedback capacitor C₁. The output V₀of the amplifier is applied to two level detectors 12 and 13 in the formof differential amplifiers supplied with detection level voltages V₁ andV₂ respectively. In the illustrated position of switch 14 V₁ is at zerovolts. V₂ is supplied by a sawtooth generator 15 synchronised to a clockpulse generator 16. The number of clock pulses in one sawtooth period islarge, say 10,000 or more.

Outputs from the detectors 12 and 13 switch a bistable device 17alternately to its two states, the switching instants being strobed bythe clock pulses. The first and second states of the bistable devicewill be defined as those two stable states to which the bistableswitches in response to V₀ attaining V₁ and V₂ respectively. In thesecond state only a gate 18 is opened and the clock pulses pass to acounter 19. Also while the bistable 17 is in the second state, a switch20, e.g. a transistor switch, is operated to apply a reference voltage-- V_(R) of opposite polarity to the input voltage V_(U) to a resistorR₂ through which a reference current then flows into the amplifier 11.In the first state of the bistable 17 the switch 20 is so operated thatzero volts is applied to R₂ and hence no current flows through R₂.

The mode of operation will be apparent from FIG. 2. At the beginning t₀of each cycle the sawtooth V₂ resets to a negative value and thenreturns linearly to zero volts, V₀ falls linearly at a rate proportionalto V_(U) and when V₀ reaches V₂ at t₁ the bistable 17 switches to itssecond state on receipt of the next clock pulse, so switching -V_(R) toR₂. V_(R) /R₂ is arranged to be larger than V_(U) /R₁ for V_(U) fullscale and therefore V₀ now rises towards V₁, reaching V₁ at t₂ when thebistable switches back to its first state. This procedure continuesuntil the end of the cycle but the reference current only has to beswitched a few times, typically 10 to 20 and switching errors are notsignificant. All cycles are identical.

If s₁ = t₁ - t₀ and s₂ = t₂ - t₁ it is apparent that s₂ /s₁ = V_(U)/(V_(R) - V_(U)), assuming that R₁ = R₂. Therefore:

s₂ /(s₁ + s₂) = V_(U) /V_(R).

But all triangles of the waveform V₀ are geometrically similar, and itaccordingly follows that

S/T = V_(U) /V_(R)

where S is the total length of all the intervals such as t₁ to t₂ inwhich the bistable is in its second state and T is the period of thecomplete cycle determined by the period of the generator 15 (and henceultimately by the clock generator 16).

Hence

V_(U) = S.sup.. V_(R) /T.

V_(r) and T are known quantities and S is given by the count in thecounter 19. S can be left in the counter for display or readout until t₁is reached in the next cycle. The minimum value for t₁ corresponding tothe full scale value for V_(U) can be determined and the counter 19 isreset within this minimum value, for example as shown off the flyback ofV₂ via a delay device 21. Part of this free time at the beginning of thecycle can be used for synchronising the generator 15. It is obviouslynot desirable to do this by frequency division right down from clockfrequency to sawtooth frequency. Instead the clock can be counted downto a frequency which is an integral multiple of that of the generator 15and the output of a comparator be used to pull the generator frequencyin known manner.

In accordance with another embodiment of the present invention, V₁ doesnot remain at zero volts but is obtained from the generator 15 byoperating the switch 14 to couple an output of the generator 15 to theV₁ input of the comparator 12. V₁ has the same period and form as V₂ butis of smaller amplitude as shown in FIG. 3, being derived, for example,from V₁ by way of a resistive potentiometer in the generator 15. Asbefore, the bistable 17 switches to its first and second states when V₀reaches V₁ and V₂ respectively. This modification has the advantage thatthe relative slopes of V₁ and V₂ can be so adjusted that, if the circuitis designed to measure a positive voltage, any fluctuating voltage whosemean value is positive with respect to ground potential can be acceptedeven though there is only a single counter 19. In known voltmeters it isnecessary to count pulses representing positive and negative portions ofthe input respectively in a differential manner (see for example theprior specification first mentioned above) unless other precautions aretaken, which may lead to errors, such as introducing a full scale offsetor using input changeover relays.

However, referring again to FIG. 3 the initial value of V₂ is madesufficiently large that, if a positive full scale voltage V_(u) actedfor the whole of T, -V_(R) will only just be able to return V₀ to zeroby opposing (and outweighing) V_(u) for the whole of the intervalcommencing when V₀ first reaches V₂ and terminating at the end of T. Onthe other hand the initial value of V₁ is made such that the slope of V₁corresponds to the slope of V₀ obtained when a negative full scalevoltage V_(u) is operative alone, i.e., not in conjunction with -V_(R).

Given these conditions, so long as V₀ reaches V₂ the mean value of V_(U)must be positive and all pulses occuring while the bistable is in itssecond state have the same sense of numerical significance. Thus, evenif V_(U) switched to its full scale negative value immediately after V₀has reached V₂ and remained at this value for the whole of the rest ofthe cycle V₀ could not reach zero volts after V₁ reaches zero volts,i.e., until the end of T. If V_(U) is negative or its mean value isnegative V₀ will never reach V₂ and the circuit will simply not read.

If bipolar inputs are to be accepted one of the well known techniquesmay be adopted, such as the use of a full scale offset or duplication ofthe level detectors 12 and 13, one pair for each polarity, each pairwith its associated bistable for controlling -V_(R) and anotherreference voltage, not shown, of magnitude equal to -V_(R) but ofopposite polarity. Note the counter 19 need not be duplicated since onlyone bistable will ever be operated and the single counter can recordmagnitude with polarity indicated from the bistable which switches toits second state.

FIG. 4 illustrates one cycle in the divergent mode of operation. Thecircuit remains as in FIG. 1 with the switch 14 set to give V₁ aconstant value of zero. The generator 15 is designed to provide in wellknown manner a sawtooth which ramps away from zero instead of towardszero as in FIG. 2. In the divergent mode a few cycles of operation arenecessary to stabilize the operation of the converter. Stabilizationoccurs when, as illustrated by FIG. 4, V₀ has the same value at the endof the cycle as at the beginning. The fact that the circuit will tendquite rapidly to this stable condition can be shown along the lines ofthe analysis appearing in the prior specification mentioned secondlyabove. Once the stable condition is reached a single cycle of period Tonly is needed for the measurement, V_(U) being given in terms of S/T asdenoted on FIG. 4, S being measured while -V_(R) is connected.

An advantage of this embodiment of the invention is that the waveform V₂can be derived by the generator 15 from the mains supply voltage so asto ensure that V_(U) is integrated over one or an integral number ofexact mains periods in order to eliminate mains jitter from the reading.It will then be desirable to synchronise the clock generator 16 with themains driven generator 15, in a manner known to those skilled in theart, rather than vice versa.

Four cycles of operation may suffice to reach the stable condition. Forexample, the generator can run at 200 Hz. (i.e. four times mainsfrequency of 50 Hz) giving a 5 m S period to each cycle and a totalmeasurement time of 20 m S. In the first and second cycles the gate 18can be kept closed so that clock pulses do not pass from the generator16 to the counter 19 and the counter 19 is not cleared at the beginningof the first cycle. Hence in the first cycle the counter displays thereading obtained in the previous measurement. In the second cycle thegenerators 15 and 16 are synchronised, for example counting up from zeroto half full house and then synchronising the phases of the generators.In the third and fourth cycles the circuit functions as heretoforedescribed to gate clock pulses into the counter so as to measure S. Thedetails given in this paragraph are also applicable to the convergentmode of operation.

Obviously many modifications can be made to the embodiments described.The clock pulses could be counted when the bistable is in its firststate instead of the second. The clock frequency need not be keptconstant. For example, to increase accuracy a lower frequency can beused at the end of the cycle with compensating stepwise adjustment ofone of the detection levels and appropriate modification of the counterso as to count each pulse with the correct significance or weightingpertaining thereto. One detection level or each of the two levels may beswitched between two discrete levels, rather than varying linearly withtime as described, or the output of the generator 15 may be arranged tobe a staircase waveform, i.e. V₂ or V₁ and V₂ would be a staircaseapproximation to a linear waveform.

Although continuous feedback is preferable through R₂ in the relevantstate of the bistable 17, to minimise switching transient errors, thefeedback can take the form, (well known in itself), of a succession ofpulses. These are only indicative of some of the possibilities formodification.

What is claimed is:
 1. An ADC comprising in combination: integrating means having an input and an output, means for applying a first electrical signal continuously throughout a measurement period to the input of said integrating means, a circuit means having two states for applying a second electrical signal opposing said first signal to the integrating means input when in one of said two states, said integrating means being responsive to the application of said first and second signals to produce an output signal at the integrating means output which ramps up and down during said measurement period as the states of said circuit means alternate, level detection means responsive to two different levels of said output signal to cause said circuit to switch alternatively to the two states thereof when the said two levels are respectively reached by said output signal, signal generator means for applying a variable waveform signal to said level detection means to cause at least one of said detection levels to vary in accordance with a predetermined function independent of the magnitude of said first electrical signal, and a clock pulse generator and counter means for counting clock pulses from said clock pulse generator while said circuit means is in one of said two states, whereby the pulses counted by said counter means are representative of the magnitude of the first electrical signal.
 2. An ADC according to claim 1, wherein said signal generator means cause one of said detection levels to vary as a periodic function of time.
 3. An ADC according to claim 1, wherein said signal generator means cause both said detection levels to vary as co-periodic functions of time.
 4. An ADC according to claim 1, wherein said signal generator means cause at least one of said detection levels to vary as a periodic, linear function of time.
 5. An ADC according to claim 1, wherein said signal generator means cause at least one of said detection levels to vary as a periodic function of time which is periodically equal in amplitude to the other detection level.
 6. An ADC according to claim 5, wherein said signal generator means cause said two detection levels to converge continuously throughout each period and to diverge from equality abruptly at the transition from one period to the next.
 7. An ADC according to claim 6, wherein at least one of said detection levels follows a linear sawtooth waveform.
 8. An ADC according to claim 5, wherein said signal generator means cause said two detection levels to diverge continuously throughout each period and to converge to equality abruptly at the transition from one period to the next.
 9. An ADC according to claim 8, wherein at least one of said detection levels follows a linear sawtooth waveform.
 10. An ADC according to claim 1, wherein said signal generator means operate periodically to cause at least one of said detection levels to vary as a periodic function of time, and wherein said signal generator means and said clock pulse generator are synchronized.
 11. An ADC according to claim 1, wherein said signal generator means operate periodically to cause at least one of said detection levels to vary as a periodic function of time and to reset said counter means to zero once in every period.
 12. An ADC according to claim 11, wherein it is arranged that each period commences with an interval in which said circuit means having two states is in that state in which clock pulses are not counted and wherein said counter means is reset during this interval but a sufficient time after the beginning of the period to allow the count accumulated in the previous period to be displayed or read out.
 13. An ADC comprising in combination: integrating means having an input and an output, level detection means responsive to and arranged to detect first and second distinct levels of an output signal at the integrating means output, a bistable device controlled by said level detection means to assume first and second states when said first and second levels are respectively attained by said output signal, means for applying an unknown electrical signal continuously throughout a measurement period to the integrating means input to cause said output signal to move from said second level to said first level when said unknown signal is the only signal applied to said input, a source of a reference signal opposing said unknown signal and responsive to the state of said bistable device to apply said reference signal to said integrating means input only while said bistable device is in said first state to cause said output signal to move from said first level to said second level, a clock pulse generator and a counter controlled by said bistable device to count clock pulses only while said bistable device is in said first state, a periodic sawtooth generator for generating waveforms of substantially sawtooth shape independent of the magnitude of said unknown signal, said periodic sawtooth generator being synchronized to said clock pulse generator such that the sawtooth waveform period at least equals a plurality of clock pulse periods, at least one of said first and second levels being provided as a sawtooth function by said sawtooth generator, whereby the total of the pulses counted by said counter when said bistable device is in said first state is representative of the magnitude of said unknown electrical signal.
 14. An ADC according to claim 13, comprising means for resetting said counter to a predetermined count a predetermined interval of time after the beginning of each sawtooth period while said bistable device is still in said second state.
 15. An ADC according to claim 13, wherein both said detection levels are provided as sawtooth functions of different amplitude by said sawtooth generator, said functions converging to equality during each sawtooth period and diverging on flyback of the sawtooth generator.
 16. An analog to digital converter comprising integrating means; means for applying an input signal to said integrating means to be integrated; first means for establishing a first reference level and for producing a first control signal when the integrated input signal reaches said first reference level; second means for establishing a second reference level for producing a second control signal when the integrated input signal reaches said second reference level; means for causing at least one of said first and second reference levels to periodically vary in magnitude independent of the magnitude of said input signal; means responsive to one of said first and second control signals for including, with said input signal as an input to said integrator, a known signal component of a polarity and magnitude to cause the integrated signal to reverse its slope, and to the other of said first and second signals for removing said known signal component; andmeans for measuring the intervals of time during which said known signal component is being integrated within an integral number of periods of variation of said at least one reference level, whereby the intervals of time measured by said means for measuring are representative of the magnitude of said input signal. 